Over the past few years, the semiconductor industry has devoted considerable attention to the use of reactive ion etching (RIE) processes for effectively mapping photoresist patterns into polysilicon thin films. In accordance with such a process, radio frequency (RF) energy is employed to excite a low pressure (e.g. 5-100 milliTorr) gas into a plasma state. This plasma is employed to create reactive species by dissociating less reactive molecules into their chemically active components (e.g. chlorine atoms from Cl.sub.2 or HCl). Reactive ion etching is distinguished from conventional plasma etching by the fact that the substrate upon which the silicon wafer being etched is mounted forms an electrode for the RF power source used to create the plasma. As such, a DC self-bias is created between the plasma and the silicon wafer, typically on the order of -150 to -350 volts. This negative self-bias establishes an electric field which accelerates the positively charged ions of the plasma in a direction normal to the surface of the substrate, whereby the ions are caused to impact the wafer surface. The ion bombardment of the surface of the wafer enhances the etch rate in the vertical direction (normal to the wafer surface) relative to the horizontal direction and results effectively in an anisotropic etch of the wafer surface.
Conventional plasma etching equipment (through which the substrate electrode is not driven and therefore does not correspond to RIE systems) does not provide this self-bias and, consequently, does not enjoy the etching enhancement provided by the ion bombardment. In the course of etching a semiconductor wafer using such conventional plasma etching equipment, in the absence of some form of sidewall masking, the wafer cannot be etched anisotropically, but instead proceeds isotropically, resulting in an undercut of the photoresist pattern and preventing attainment of a precise small geometry topography.
Although the anisotropic etching capability of RIE equipment is generally desirable, it can create problems when used in conjunction with certain topographies. An example of such a topography involves direct moat wafer processing in which a field oxide, that is formed on the planar surface of a substrate and is used to prevent the creation of unwanted parasitic devices beneath overlying interconnect material, has formed therein apertures or windows through which dopants for forming device regions are introduced, and within which gate electrodes are to be provided.
An illustration of an exemplarily embodiment of an apertured field oxide layer for forming a field effect device in a semiconductor (e.g. silicon) substrate using such processing is shown in FIGS. 1-8, of which FIGS. 1, 3, and 5 are plan views of the device while FIGS. 2, 4 and 6 are sectional views along line A-A' of FIGS. 1, 3, 5, respectively. FIG. 7 is a sectional view taken along line B-B' of FIG. 5, while FIG. 8 is a sectional view taken along line C-C' of FIG. 5. As shown in FIGS. 1 and 2, a (silicon) substrate 10 having a planar surface 11 has a field oxide layer 12 formed thereon (typically to a thickness on the order of 5,000-8,000.ANG.). Field oxide layer 12 has an aperture or window 13 formed therein exposing a surface region 14 of the planar surface 11 of substrate 10. The sidewalls 15 of window 13 are effectively perpendicular to planar surface 11, so as to allow subsequent formation of an insulative spacer thereat.
Next, as illustrated in FIGS. 3 and 4, following the formation of a thin dielectric (gate oxide) layer 21 (having a thickness on the order of 100-400.ANG.), gate electrode material (e.g. doped polysilicon) 25 is nonselectively formed on the top surface 16 of the field oxide layer 12 and on the thin gate oxide layer 21 within the entirety of the aperture 13. Many methods of polysilicon deposition (e.g. low pressure chemical vapor deposition (LPCVD)) provide a conformal film (layer 25) that has the same film thickness over the vertical and horizontal features of the topography upon which it is formed. This conformal film results in a vertical film thickness T at the step of the field oxide 12, which is equal to the film thickness t in the areas overlying the field oxide plus the height of field oxide step itself.
Layer 25 of the polysilicon gate material is then selectively etched anisotropically to form a gate electrode layer 26 which, as shown in FIGS. 4 and 6, overlies the top surface 16 of field oxide layer 12 and extends onto the thin gate oxide layer 21. During this step, that portion of the polysilicon layer 25 whereat the gate electrode 26 is to be formed is masked and the exposed polysilicon material is reactive ion etched, so as to remove the polysilicon layer in a direction normal to the surface 11 of the substrate 10 down to the surface of the field oxide layer 12 and substrate surface 11, partially removing exposed surface portions of the thin gate oxide layer 21 adjacent to the masked polysilicon gate 26 and the field oxide layer 12. Complete removal of the gate oxide layer 21 would result in etching of the substrate 10 which is unacceptable from a standpoint of the final device configuration.
More particularly, the anisotropic etch of the polysilicon proceeds until a thickness t as shown in FIG. 4 is removed. At this point, the gate oxide layer 21 becomes exposed to the etch environment. Once exposed, the gate oxide 21 begins to etch. Should all of the gate oxide 21 be etched away, the etch will proceed into the silicon substrate 10 and effectively destroy the device. Stopping the etch before this complete removal of the gate oxide occurs will, for typical values of gate and field oxides, leave some of the polysilicon having a thickness equal to the oxide wall height around the oxide wall as shown at region 30 in FIGS. 7 and 8. This residual thickness is commonly referred to as a stringer and constitutes a severe problem, as it effectively connects adjacent devices together with the conducting polysilicon material.
If an attempt is made to remove the stringer by continuing the etch, a percentage overetch equal to the step height divided by the film thickness t in the horizontal areas is required (e.g. if the step height is 8,000.ANG. and the film thickness t is 5,000.ANG., then a 160% over etch would be required to clear the polysilicon stringer 30).
Chlorine chemistries (e.g. Cl.sub.2, HCl, or BCl.sub.3) are often chosen for etching polysilicon because of their higher selectivity to oxide than that easily achieved using a florine chemistry. See, for example, an article entitled "Anisotropic and Selective Reactive Ion Etching of Polysilicon using SF.sub.6 " by P. Parrens, J. Vac. Sci. Technol. Vol. 19, No. 4, pg. 1403 (1981). Selectivity of etch is defined as the ratio of the etch rate of the film that is preferentially etched to the etch rate of the underlying film. For example, a polysilicon etch rate that is twenty times faster than the etch rate of the underlying oxide film would result in a selectivity of twenty, a value which is typical of a moderate selectivity chlorine chemistry reactive ion etch. If such a long overetch is attempted with an etch material that has only moderate selectivity to oxide, the thin gate oxide layer would be completely removed and the underlying silicon in the active device areas would be etched, resulting in destruction of the device. For example, in the configuration shown in FIGS. 1-8 above, if the thickness of the gate oxide layer 21 is on the order of 200.ANG., then, in order to leave a safe amount of gate oxide (100.ANG.) after removal of stringer 30, a selectivity of 80 would be required.
While it is possible to remove the stringer isotropically using a (non-RIE) plasma etch, such a process would result in undercutting of one film thickness per side of photoresist, or a total loss of two film thicknesses per line. For example, with a 5,000.ANG. polysilicon film thickness, the total linewidth loss would be 10,000.ANG. or 1 micron using an isotropic etch. Such a loss is unacceptable in the fabrication of narrow line width topographies.
As described in an article entitled "Anisotropic Plasma Etching of Polysilicon" by C. J. Mogab and H. J. Levinstein, J. Vac. Sci. Technol., Vol 17, No. 3, pg. 721 (1980), an anisotropic plasma etch employing sidewall protection chemistry requires the same high selectivity as anisotropic reactive ion etch in order to remove the unwanted polysilicon stringer 30 without etching through the gate oxide layer 21.
High selectivity (50-100) etches using unusual gases (expensive, and not normally employed in standard polysilicon etching processes) have been reported in articles such as "Anisotropic Plasma Etching of Polysilicon with 100:1 Selectivity over Thermal Oxide" by D. B. Rao in SPIE Vol. 470, "Optical Microlithograph III: Technology for the Next Decade", pg. 39 (1984) and "Highly Selective Dry Etching of Polysilicon Using Chlorinated Gas Mixtures for VLSI Applications" by E. Degenkolb et al, J. Electrochem Soc.: Solid-State Science and Technology, Vol. 132, No. 8, pg. 2207 (1985). However, because of their high selectivity, such etches have difficulty in penetrating the thin native oxide which forms on the top surface of the polysilicon when exposed to air. This difficulty results in a prolonged initiation of the polysilicon etch and, because the native oxide is not of uniform thickness, different regions of the oxide are removed at different points in time on the surface the wafer. This nonuniformity results in the polysilicon areas which are first exposed beginning to etch 50-100 times faster than areas still covered by the native oxide, thereby transferring and enlarging the non-uniformities in the original native oxide into the polysilicon film.
A further complication of the process is due to the impact of the impurity doping concentration of the polysilicon film upon the etch rate. Polysilicon films having high N-type dopant (e.g. arsenic or phosphorus) concentrations (namely having sheet resistivities on the order of 10-30 ohms per square) etch at a much higher rate than lightly or undoped polysilicon. In fact, this etch rate enhancement of doped polysilicon can be more than twice that of an undoped film. A side effect of this faster etch rate is that it reduces the ratio of the vertical etch rate in the open areas (exposed to the reactive ion etch bombardment) to the horizontal etch rate in the areas covered by the photoresist. This ratio reduction results in a less anisotropic etch and greater undercut of the photoresist pattern.